The present invention relates to a semiconductor device, and more particularly to an improved interconnection layer structure in a semiconductor integrated circuit device having macro cell regions and a method of forming the same.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of the conventional semiconductor device having a macro cell region a circuit region wherein interconnection layers having a uniform thickness and extend across the macro cell region and the circuit region.
A macro cell and a peripheral circuit region are monolithically integrated on a semiconductor substrate 1. A field oxide film 2 is selectively formed on a surface of the semiconductor substrate 1 at the boundary between the macro cell region and the peripheral circuit region. Both in the macro cell region and the peripheral circuit region, a plurality of field effect transistors are formed on the surface of the semiconductor substrate 1. Gate oxide films 3 having a thickness of 65 angstroms are formed on the surface of the semiconductor substrate 1. Gate electrodes 4 are formed on the gate oxide films 3. The gate electrodes 4 comprise polysilicon films having a thickness of 1500 angstroms. Side wall oxide films 5 are provided at opposite sides of each of the gate electrodes 4 to form lightly doped drain structures.
A first inter-layer insulator 6 is entirely formed over the semiconductor substrate 1 so that the first inter-layer insulator 6 covers the gate electrodes 4 of the field effect transistors. The first inter-layer insulator 6 is made of silicon oxide and boron-phosphate silicate glass. Contact holes 7 are selectively formed in the first inter-layer insulator 6. The contact holes 7 are filled with a refractory metal, for example, tungsten 8a. The first inter-layer insulator 6 has a top surface planerized across the macro cell region and the peripheral circuit region. First interconnection layers 9a and 9b are selectively formed which extend across the macro cell region and the peripheral circuit region. The first interconnection layers 9a are located in the macro cell region and the first interconnection layers 9b are located in the peripheral circuit region.
The first interconnection layers 9a and 9b have a uniform thickness and comprises laminations of a titanium layer 18a having a thickness of 300 angstroms, a titanium nitride layer 19a having a thickness of 1000 angstroms, an aluminum layer 20a having a thickness of 3000 angstroms, a titanium nitride layer 19b having a thickness of 500 angstroms, an aluminum layer 20b having a thickness of 3000 angstroms, and a titanium nitride layer 19c having a thickness of 500 angstroms.
The first interconnection layers 9a and 9b are connected via the contact holes 7 filled with the tungsten 8a to the field effect transistors. The first interconnection layers 9a located in the macro cell region has the same width as the first interconnection layers 9b located in the peripheral circuit region, for example, the width of the interconnection layers 9a and 9b is 0.3 micrometers. Over the macro cell region and the peripheral circuit region, the first interconnection layers 9a and 9b are arranged in parallel to each other at a constant pitch of 0.4 micrometers in consideration of facilitated circuit layout design. As a design modification, it is however possible to arrange the first interconnection layers 9a and 9b at various pitches or different pitches across the macro cell region and the peripheral circuit region.
A second inter-layer insulator 10 is entirely provided over the first inter-layer insulator 6 so that the second inter-layer insulator 10 covers the first interconnection layers 9a and 9b. The second inter-layer insulator 10 is made of silicon oxide and deposited by a plasma chemical vapor deposition method. The second inter-layer insulator 10 has a top surface planerized across the macro cell region and the peripheral circuit region. Via holes 11 are selectively formed in the second inter-layer insulator 10. A barrier metal layer 12 is formed on the bottom and side wall of each of the via holes 11 as well as selectively formed over the top surface of the second inter-layer insulator 10. The barrier metal layer 12 comprises laminations of a titanium nitride film having a thickness of 1000 angstroms and a titanium film having a thickness of 300 angstroms. Each of the via holes 11 coated by the barrier metal layer 12 is filled with a tungsten 8b. Second interconnection layers 13a and 13b are provided on the second inter-layer insulator 10. The second interconnection layers 13a are located in the macro cell region, whilst the second interconnection layers 13b are located in the peripheral circuit region.
The second interconnection layers 13a and 13b have a uniform thickness and comprises laminations of a titanium layer 18a having a thickness of 300 angstroms, a titanium nitride layer 19a having a thickness of 1000 angstroms, an aluminum layer 20a having a thickness of 3000 angstroms, a titanium nitride layer 19b having a thickness of 500 angstroms, an aluminum layer 20b having a thickness of 3000 angstroms, and a titanium nitride layer 19c having a thickness of 500 angstroms.
The thickness of the second interconnection layers 13a located in the macro cell region is the same as the thickness of the second interconnection layers 13b located in the peripheral circuit region. A cover layer 14 is further provided which covers the second interconnection layers 13a and 13b. The cover layer 14 is made of silicon oxide nitride, SiON.
FIGS. 2A and 2B are fragmentary cross sectional elevation views illustrative of sequential processes involved in a method of forming the conventional semiconductor device of FIG. 1.
FIG. 3 is a fragmentary cross sectional elevation view illustrative of the other conventional semiconductor device having a macro cell region and a circuit region wherein interconnection layers having a uniform thickness extend across the macro cell region and the circuit region.
The above conventional semiconductor device has the following disadvantages. In the conventional semiconductor device, the interconnection layer has a uniform thickness across the macro cell region and the peripheral. Normally, the lengths of the interconnection layers in the macro cell region are shorter on the average than the lengths of the interconnection layers in the peripheral circuit region. Since the averaged lengths of the interconnection layers in the macro cell region are relatively short, no serious problem with increase in the resistance of the interconnections is raised in the macro cell region even though the thicknesses of the interconnection layers are reduced. However, a reduction in the thickness of the interconnection layers increases resistance of the interconnections in the peripheral circuit region, causing a delay of the signal transmission on the interconnections in the peripheral circuit region. On the other hand, if a sufficient thickness is kept for the interconnection layers, then the interconnection capacitance increases between adjacent two interconnections, resulting in a time-delay of signal transmission on the interconnections in the macro cell region.